1. Field of the Invention
This invention relates to the field of current mirrors, and particularly to precision chopper-stabilized current mirrors.
2. Description of the Related Art
Current mirrors are widely used in analog circuit design. Some applications require a mirror that is highly accurate; i.e., with an output current (Iout) to input current (Iin) ratio that is precisely known.
A simple two-transistor current mirror may not be able to provide a desired accuracy, due to the difficulty in precisely matching the two transistors. To mitigate errors that might otherwise arise due to transistor mismatch, a chopped current mirror is often employed; the operation of such a mirror is illustrated in FIGS. 1a–1c. The mirror operates with a two-phase chopping cycle. FIG. 1a shows the mirror's operation during the first phase: field-effect transistor (FET) M1 is diode-connected and mirrors an input current (Iin) to FET M2, which produces an output current Iout1. During the second chopping phase (FIG. 1b), M1 and M2 are interchanged: M2 is diode-connected and mirrors Iin to M1, which produces an output current Iout2.
Though a chopped mirror reduces mismatch errors, they are not completely eliminated. Assume the current conducted by M2 mismatches that conducted by M1 by a ratio of (1+x), and that M1 and M2 are interchanged at a 50/50 duty cycle. The average output current Iout will be given by (assuming a 50/50 duty cycle):
      I    out    =                    I        out1            +              I        out2              2  Iout1 is given by:Iout1=Iin(1+x),and Iout2 is given by:
      I    out2    =                    I        in            ⁡              (                  1                      1            +            x                          )              .  Therefore, the mismatch (x) results in an error between Iin and Iout given by:
      I    out    =                    I        in            ⁡              (                  1          +                                    x              2                                      2              +                              2                ⁢                x                                                    )              .  If mismatch x is small:
      I    out    ≅                    I        in            ⁡              (                  1          +                                    x              2                        2                          )              .  
The operation of the current mirror is visible in FIG. 1c, which depicts Iout1 and Iout2 with respect to Iin during each phase of the chopping cycle. Other errors may arise due to, for example, parasitic capacitances present on the drains of the mirror transistors, device mismatches, and output impedance mismatches, which can produce an output offset error. Also, when the circuitry driving the chopped mirror is also chopped, timing-related errors may arise if the mirror and the driving circuit are chopped synchronously.